Advanced Process Technologies, Packaging, and Design Flow
Taipei, Taiwan, May 19, 2025 (GLOBE NEWSWIRE) — Alchip Technologies Limited, a leader in high-performance and AI infrastructure ASICs, today unveiled a comprehensive design and manufacturing ecosystem supporting NVIDIA’s NVLink Fusion. This ecosystem integrates advanced process technologies, proven packaging options, and the industry’s most flexible engagement model.
The announcement follows NVIDIA’s Computex introduction of NVLink Fusion, a silicon solution enabling hyperscalers to build custom compute systems with the world’s most advanced computing fabric and rack-scale architecture. Alchip was highlighted as one of NVLink Fusion’s first adopters.
Alchip’s NVLink Fusion ecosystem includes its 2nm and 3nm Design Platforms, industry-leading 3DIC technology portfolio, and customizable design flow. Alchip has achieved a record number of 3nm tape-outs and is actively engaging customers with its groundbreaking 2nm Design Platform. This platform supports the physical design of 2nm chips using various 2.5D/3D technologies, including CoWoS-S, CoWoS-R, and CoWoS-L. It also facilitates the development of IO chiplets that work with 2nm and 3nm compute dies, offering Die-to-Die IP and IO chiplet design capabilities.
Alchip’s silicon-proven 2.5D and 3D design flow, part of the NVLink Fusion ecosystem, optimizes essential flows such as power delivery, Die-to-Die electrical interconnect, and system-wide thermal characterization.
The new 3DIC design flow’s power delivery module includes power integrity, power grid design (with through-silicon via distribution), and power integrity simulation and sign-off capabilities. Die-to-Die electrical interconnect capabilities address low clock skew across dies, process variation immunity, noise immunity, data transmission across different power domains, and inter-die setup/hold timing margin. The design flow also covers thermal characterization to enhance power density, perform 3D non-uniform power mapping, mitigate 3D thermal crosstalk effects, and model package and system cooling solutions.
Alchip’s design methodology reduces turnaround time for both design implementation and verification by proactively addressing side effects before floor planning and clock/power planning stages. AI-related ASIC designs span package, substrate, and testing. These ‘last-mile’ services are crucial for AI-driven and high-performance computing companies seeking maximum return on their substantial investments.
“NVLink Fusion is a complete Alchip offering for XPU development. Alchip is committed to fully supporting this solution for its customers,” said Erez Shaizaf, CTO of Alchip Technologies.
About Alchip
Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global High-Performance Computing and AI infrastructure ASIC provider of IC and packaging design, and production services for companies developing complex and high-volume ASICs and SoCs. Alchip provides faster time-to-market and cost-effective solutions for SoC design at mainstream and advanced process technology. Alchip has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3D CoWoS packaging, chiplet design, and manufacturing management. Customers include global leaders in artificial intelligence, high-performance computing, supercomputing, mobile communications, entertainment device, networking equipment, and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661).
For more information, please visit our website: http://www.alchip.com
CONTACT: Charles Byers Alchip Technologies + (408)-310-9244 chuck_byers@alchip.com
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